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SSPD_Chapter 7_Part 7_Scaling of MOS circuits_concluded.

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: SSPD_Chapter 7_Part 7_Scaling of MOS circuits_concluded. gives the definition of half-pitch and node. It gives limitation posed by Interconnect delays and the ways to overcome them. It gives importance of thermal management because of exponentially growing dissipation per die with scaling. It also gives the new challenges being posed due to scaling especially the sub-threshold leakages and the use of High K-metal to overcome it.

SSPD_Chapter 7_Part 7_Scaling of MOS circuits_concluded.

7.7.8. Definition of half pitch and node.

International Technology Roadmap for Semiconductors uses ‘node’ to refer to the smallest feature size on Logic Chips. This is the length of the Gate of MOSFET. Whereas in Memory Chips ‘half pitch’ is used to define the smallest feature size.

Half-pitch is the half distance between two adjacent aluminium pathways. Nodes and half-pitch are illustrated in Figure 7.7.8.1

Figure 1
Figure 1 (Picture 1.png)

As is evident from the figure, Half-Pitch = Node. But with the evolution of Technology the MOS structure has been modified and today Half-Pitch > Node. In Figure 7.7.8.2 we see the evolution of MOS structure from 1970 to 2005.

As we see that with scaling LDD(Lightly Doped Drain) had to be introduced under the edges of the Gate to mitigate the short channel effect. With the scaling of the dimensions, VDD was not proportionately scaled down under General Scaling Scheme as a result sharp electric field is created which results in “hot electrons effect”. Hot Electron Effects has deleterious effects on the Device. These are the following:

  1. It injects electrons into the oxide layer leading to instability of the device.
  2. It limits the velocity to scatter limited velocity which in effect saturates the electron velocity and we forfeit the advantage of reduction in transit delay with scaling. In long channel devices transit delay scales down by 1/α in constant field scaling and by 1/α2 in constant voltage scaling.
  3. In short channel when electron velocity saturates , we can obtain the scale down by 1/α in constant field scaling but we cannot obtain 1/α2 scaling in constant voltage scaling.
  4. Also under short channel effect channel length modulation parameter gets aggravated.
Figure 2
Figure 2 (Picture 3.png)

To mitigate the short channel effects we introduce Side-Wall Spacer at the edges of the Poly-Si Gate and LDD(Lightly Doped Drain) on source and drain side as shown in the lower half of Figure 7.7.8.2.. LDD extends below the the edge of the Poly-Si Gate. This has been achieved by tilted angle implant.

By grading the doping of Drain and Source from N+ to N- (LDD), we allow a more gradual drop of voltage leading to the reduction in the peak of the electric field along the channel. Even modest reduction in field leads to significant improvement in the performance of the device. It suppresses the hot electron generation, it prevents the saturation of the drift velocity of the electrons in the channel and the shallow junction of LDD helps minimize the chanel length modulation parameter.

The net result of this modification has been that in recent years Half-Pitch > Node as seen in the following tables.

In Table 7.7.8.1 we give the scaled down dimensions of MOSFET over the last 4 decades.

Table 7.7.8.1.Dimension Scaling in MOSFET over the last 4 decades.

Table 1
Year 1967 1997 1999 2001 2003 2006
L(μm) 10 0.25 0.18 0.13 0.1 0.07
DRAM(Gbit/cm2) 64M 0.18 0.38 0.42 0.91 1.85
Jn.Depth(xj nm) 1000 100 70 60 52 40
Interconnection Pitch(nm) 2000 600 500 350 245 130

In Table 7.7.8.2. we give the scaling in terms of Half-Pitch and Node.

Table 7.7.8.2. Evolution of Nodes and Half-Pitch with advancing Generations.

Table 2
Year Node(nm) Half-Pitch(nm) Gate Length*(nm)
2009 a 32 52 29
2007 a 45 68 ?
2005 b 65 90 32
2004 b 90 90 37
2003 b 100 100 45
2001 c 130 150 65
1999 c 180 230 140
1997 d 250 250 200
1995 d 350 350 350
1992 d 500 500 500

a-ITRS data 2008 update.

a-ITRS data 2006

a-ITRS data 2001

a-ITRS data 1997

*The physical length has become smaller than the printed length.

7.7.9.Limits due to Interconnection.

In Figure 7.7.9.1 we have defined the width(W), thickness(t) and spacing (S) of the metal pathway/metal interconnection at the same level and height (h)of the oxide layer separating two adjacent level metal pathways.

Figure 3
Figure 3 (Picture 4.png)

We have two scaling models. One model is fixed thiockness and the other is scaled thickness.

Wire length will be short for ‘local innterconects’ and will be chip long for ‘global interconnects’.

Die size will be scaled by DC = 1.1. As we scale down, the die size is scaled up so as to build more and more complex ‘System-on-Chip’.

In Table 7.7.9.1 we give the performance of local and global interconnects.

Table 7.7.9.1. Influence of Scaling on Interconnect Characteristics.

Table 3
Parameter ___________ Var.’t’ Const.’t’
Width(W)   1/S 1/S
Spacing(S)   1/S 1/S
Thickness(t)   1/S 1
Interlayer Oxide height(h)   1/S 1/S
Characteristics per unit length      
Wire Resistance per unit length RW=1/(Wt) S2 S
Fringing Cap.per unit length CWf=t/S 1 S
Parallel Plate Cap.per unit length CWp=W/h 1 1
Total Wire Cap per unit length CW= CWf+ CWp 1 1 to S
Unrepeated RC per unit length tWU= RW CW S2 S to S2
Repeated RC per unit length* tWR=√(RC RW CW) √S 1 to √S
Cross Talk (Noise) t/S 1 S
Local/scaled Interconnect Delay      
Length(L) L 1/S 1/S
Unrepeated Wire RC delay L2tWU 1 1/S to 1
Repeated Wire RC delay LtWR 1/√S 1/S to 1/√S
Global Interconnect Delay      
Length(Chip length) L DC DC
Unrepeated Wire RC delay L2tWU S2DC2 SDC2to S2DC2
Repeated Wire RC delay LtWR DC√S DC to DC√S

*Asuming constant field scaling of gates.

7.7.9.1.Interconnect Delays are limiting the performance with advanced Generations of Technology

Inspection of Table 7.7.9.1 leads us to the following conclusions

  1. Wire Capacitances per micron is remaining constant at 0.2femto Farads/μm. This is roughly 1/10 of gate capacitance;
  2. Local wires are getting faster but not quite as fast as the Gates but that is not a major problem.
  3. Global wires are getting slower.

In Figure 7.7.9.1 we make a comparative study of the Gate Delays, Interconnect delays and the overall delay. We clearly see a minimum dealy of 12 psec at Node 250nm for Al and SiO2 and a minimum delay of 8 psec at Node 180nm for Cu and low-K interconnect. This is the reason why IBM has completely switched over to Copper and low-K interconnects.

Figure 4
Figure 4 (Picture 6.png)

7.7.9.2.Ways and means for overcoming the Interconnect Bottleneck of cost and performance.

Some of the logical solutions for overcoming the Interconnect bottleneck are:

  1. More levels of interconnect. We had to resort to 7to 8 levels of metallization at 100nm Node.
  2. Hierarchy of design rules for local, semi-local and global routing.
  3. Once the practical limits have been achieved we can further improve by going for Copper interconnects and low refractory index dielectric materials for higher propogation velocity. These dielectrics could be organic or aerogols.

7.7.10. Thermal Management due to excessive heating consequent to scaling.

Scaling reduces power dissipation per Gate but scaling increases the number of gates per chip. This coupled with higher speed scales up Chip Power Dissipation. Therefore Thermal Management becomes the central theme of Advanced Electronic Systyems.

In 1960, we had SSI chips which dissipated 0.1W to 0.3W per chip. These were cooled by Air and Liquid Cooling Techniques.

In 1980 we had BJT LSI and CMOS VLSI chips which dissipated 1 to 5W.

In 1990 CMOS VLSI were dissipating 15 to 30 W of heat.

CMOS μP chips at 1 to 2 W level were managed by heat sinks and heart spreaders.

When the dissipation level reached 2 to 3 W/cm2 totalling to 300W at substrate level in multi-chip modules there we went for Liquid cooling.

Water cooled multi-chip modules evolved to refined indirect liquid cooling designs.

In 1990, third generation cooling modules were introduced which could handle 2 to 5kW dissipation in 225 to 1000cm2 footprint.

7.7.10.1.Methods of Cooliing .

Some of the popular methods of cooling which were adopted were:

  1. Compact heat exchangers;
  2. Miniature refrigerators in Si – cooling system was imntegrated with the chip.
  3. Direct liquid cooling of bare chips.
  4. Chip packages in dielectric liquid;
  5. In late 1980s, low cost , air-cooled multi-chip modules became popular. These had spatial and volumetric cooling facilities.
  6. Water cooled modules were also developed.

The method of cooling was categorized according to the product categories.

  • Low cost electronic systems costing less than $300 had bouyance, induced natural circulation of air method of cooling.
  • Handheld equipments costing less than $1000 had heat spreaders. This would suffice for 1 to 2 W ICs.
  • Desktop and note-books computers costing less than $3000 had several options.
    • One option was heat sink with air-cooling.
    • Second option was cooling by remotely located fans.
    • Third option was Fan cooled heat sinks.
    • Fourth was natural convecting air, circulating past low-fin heat sinks, heat pipes and metal cases. This sufficed for 3 to 5W per chip dissipation.
  • High performance Systems costing more than $3000 had forced cooling systems.
  • The harsh environment had still more elaborate methods of cooling.

By 1997, IC power dissipation reached 100 to 150 W heatdissipation. Chip back side is allocated to heat removal. The heat removal may be done by any one of the following methods:

  • Conducting away the heat through solids with high thermal conductivity;
  • Through convection the heat is removed;
  • Through pumped liquid transport.
  • Throuugh Vapour diffusion.

Thermal and Thermofluid modeling software is being accepted for simulation based development and implementation of advanced packages. High performance, air-cooled heat sinks will dominate future applications.

7.7.11.The Challenges being posed by Scaling.

7.7.11.1. High-K dielectric for Gate Insulation.

The biggest challenge is the unacceptably thin gate oxide with advanced scaling.

Table 7.7.11.1 gives the thicknesses of gate oxide with advanced Generation of MOS devices.

Table 7.7.11.1. The Gate Oxide Thickness (D nm) in advanced Generations of Devices.

Table 4
Generation 5μm 2μm 1.2μm 90nm 45nm 30nm
D(nm) 88nm 40nm 22nm 1.3nm ? ?

We see that as we reach 90nm Generattion of Devices, the oxide layer becomes:

Figure 5
Figure 5 (graphics1.png)

At 5 atomic layer thick Gate Oxide direct Quantum Mechanical tunneling is enabled leading to high Gate leakage and increased static power dissipation. The only solution was to make it physically thick but keep it electrically thin so that threshold voltage is unaffected., So we go for high K dielectric material for gate insulation.

Since Gate Capacitance has to remain constant therefore:

Figure 6
Figure 6 (graphics2.png)

Therefore:

Figure 7
Figure 7 (graphics3.png)

So if a high K material 5× the dielectric constant of SiO2 is used we will have 5× thick oxide layer that is 6.5nm thick dielectric material at the Gate which will completely cutoff the leakage and hence we normalize the statric power dissipation to nW in CMOS logic..

High K dielectrics are HfO2 with K=15 to 30 or HfSiO2 with K= 12 to 16..

7.7.11.2. Poly-Silicon Gate should be replaced by Metal as Silicon Dioxide replaced by High-K insulator.

The scaling forces SiO2 to be replaced by high-K insulator but it simultaneously demands Poly-Si to be replaced by Metal. As we progress with scaling Poly-Si becomes less effective as Gate. There are three reasons for this:

  1. Because of Fermi-level pinning we get higher threshold voltage;
  2. High-K material has high elasticity hence results in higher phonon or lattrice scattering. This results in the deterioration of channel conductivity;
  3. Poly-Si has poor bonding with high-K insulator.

Therefore Poly-Si has to be replaced by Metal again as it was in the start of IC

Technology.

7.7.11.3.Strained Silicon for enhanced channel mobility.

To further solve the problem of reduced channel mobility, Uniaxial Process induced Stress could be used for enhanced mobility and hence for higher channel conductivity.

7.7.12. Concluding Remarks on Scaling.

Table 7.7.12.1. gives the typical scaling factors which have been used for the advanced Generations of the Devices.(Reference:”Device Scaling:The Treadmill that fuelled Semiconductor Industry Growth” by Pallab Chatterjee, i2 Technologies, Inc.)

Table. 7.7.12.1.Semiconductor Association Association 1992 Overall Road Map Technology Characteristics.

Table 5
  1992 1995 1998 2001 2004 2007
Node(2λ) nm 500 350 250 180 120 100
Scaling factor(α) - 1.43 2 2.8 4.16 5
Desktop,VDD(V) 5 3.3 2.2 2.2 1.5 1.5
Portable,VDD(V) 3.3 2.2 2.2 1.5 1.5 1.5
Desktop, (β) - 1.515 2.27 2.27 3.33 3.33
Portable, (β) - 1.5 1.5 2.2 2.2 2.2
High Per.-PD(W per die) 10 15 30 40 40-120 40-200
Portable.-PD(W per die) 3 4 4 4 4 4
Clock(MHz)-off chip 60 100 175 250 350 500
Clock(MHz)-on chip 120 200 350 500 700 1000
f0 is scaled by α2/β-offchip 60 81 105 207 312 450
f0 according to SIA 60 100 175 250 350 500
f0 is scaled by α2/β-on-chip 120 162 211 414 623 901
f0 according to SIA 120 200 350 500 700 1000
Power per die(W) 10 15 30 40 80 120
No. of Gates per die(SIA) 300k 500k 2M 5M 10M 20M
Pg(power per gate)×10-5W 3.33 3 1.5 0.8 0.8 0.6

In addition to speed and packing density, scaled CMOS provides new opportunities in low power management. Speed can be traded off fiir reduction in power consumption.

40N. AA NiMH Battery Cells are required for FULL MOTION VIDEO PLAYER in 0.5μm technology.

1No. AA NiMH Battery Cells are required for FULL MOTION VIDEO PLAYER in 0.1μm technology.

This gives the kind of accessibility which can be developed for the electreonic goods with Scaling.

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